"I love GitHub - crossroadsfpga/pigasus: 100Gbps Intrusion Detection and Prevention System"

2022-06-22 01:59:00

Skip to content Signup Product Features Mobile Actions Codespaces Copilot Packages Security Code review Issues Integrations GitHub Sponsors Customer stories Team Enterprise Explore Explore GitHub Learn and contribute Topics Collections Trending Skills GitHub Sponsors Open source guides Connect with others The ReadME Project Events Community forum GitHub Education GitHub Stars program Marketplace Pricing Plans Compare plans Contact Sales Education Sign in Sign up {{ message }} crossroadsfpga / pigasus Public Notifications Fork 64 Star 586 100Gbps Intrusion Detection and Prevention System 586 stars 64 forks Star Notifications Code Issues 2 Pull requests 2 Actions Projects 0 Wiki Security Insights More Code Issues Pull requests Actions Projects Wiki Security Insights crossroadsfpga/pigasus This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository. main Switch branches/tags Branches Tags Could not load branches Nothing to show {{ refName }} default View all branches Could not load tags Nothing to show {{ refName }} default View all tags 2 branches 1 tag Code Latest commit jhoecmu Update README.md … 38bd76b May 22, 2022 Update README.md 38bd76b Git stats 60 commits Files Permalink Failed to load latest commit information. Type Name Latest commit message Commit time docs/developers_meeting Add next dev meeting agenda Feb 25, 2022 fluid Support non-constexpr widths for extern signals in VTL Mar 16, 2022 pigasus Added assertion to enforce eSRAM block capacity limit Mar 21, 2022 pigasus_multi Bug-fix: remove hardcoded widths used in pktbuf addressing Mar 16, 2022 README.md Update README.md May 22, 2022 pigasus.py Bug-fix: remove hardcoded widths used in pktbuf addressing Mar 16, 2022 pigasus_logo.png init commit Sep 5, 2020 pigasus_multi.py Bug-fix: remove hardcoded widths used in pktbuf addressing Mar 16, 2022 pigasus_release.md init commit of Pigasus 2.0 Nov 3, 2021 run_pigasus.sh init commit of Pigasus 2.0 Nov 3, 2021 run_pigasus_multi.sh init commit of Pigasus 2.0 Nov 3, 2021 services.gv.png init commit of Pigasus 2.0 Nov 3, 2021 top0_base.sv init commit of Pigasus 2.0 Nov 3, 2021 top1_base.sv init commit of Pigasus 2.0 Nov 3, 2021 top_base.sv init commit of Pigasus 2.0 Nov 3, 2021 View code Pigasus 2.0 Customize Pigasus License README.md Pigasus 2.0Pigasus is an Intrusion Detection and Prevention System (IDS/IPS) that achieves 100Gbps using a single FPGA-equipped server. Pigasus' FPGA-first design ensures that most packets are processed entirely using the FPGA, while some packets are sent to the CPU for full evaluation. Refer to the OSDI '20 paper and Zhipeng Zhao's PhD Thesis for details about the design. You can view a presentation by Zhipeng on the Crossroads YouTube Channel.Compared to Pigasus 1.0, Pigasus 2.0 enables easy customization and more efficient scaling of the Pigasus design. For more details, please refer to the Pigasus_Release.If you want to run Pigasus as it is, without customization, please go to ./pigasus directly.Customize PigasusInstructions for customizing Pigasus 2.0 (what most users should need) are available in the comments of pigasus.py. After modifying that file run run_pigasus.sh to regenerate the Pigasus 2.0 RTL code in ./pigasus with modifications. Similarly, to customize multi-FPGA Pigasus 2.0 edit pigasus_multi.py and then run run_pigasus_multi.sh to regenerate the multi-FPGA Pigasus RTL code in ./pigasus_multi with modifications. There is also a tutorial.Directory organizationrun_pigasus.sh: driver script for generating Pigasus. This is what most users should need.run_pigasus_multi.sh: driver script for generating multi-FPGA Pigasus.pigasus: contains the RTL code for single-FPGA Pigasus' modules. See Pigasus README for RTL simulation instructions.pigasus_multi: contains the RTL code for multi-FPGA Pigasus' modules. See Pigasus Multi README for RTL simulation instructions.pigasus.py: front end to drive Fluid for constructing Pigasus 2.0 designs. The comments in this file mention how to customize Pigasus 2.0 by editing this file.pigasus_multi.py: front end to drive Fluid for constructing multi-FPGA Pigasus 2.0 designs. The structure of this file is similar to pigasus.py, therefore the documentation is the same and is only present in pigasus.py.fluid: contains a minimal version of Fluid for constructing Pigasus 2.0 designs. See Fluid README for more information.top_base.sv, top0_base.sv, top1_base.sv: helper SystemVerilog code for generating new Pigasus 2.0 designs.LicensePigasus is developed at Carnegie Mellon University. The software component (pigasus/software) is adapted from Snort3 and released under the GNU General Public License v2.0. The rest of the components including (pigasus/hardware,pigasus_multi_fpga,fluid) are released under the BSD 3-Clause Clear License. About 100Gbps Intrusion Detection and Prevention System Resources Readme Stars 586 starsWatchers 31 watchingForks 64 forks Releases 1 v1.0 Latest Feb 10, 2022 Packages 0 No packages published Contributors 8 Languages C++ 68.2% SystemVerilog 17.0% HTML 6.3% C 2.5% Tcl 2.4% Python 1.1% Other 2.5% © 2022 GitHub, Inc. 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